64M x 16 Bit x 8 Banks DDR3(L) SDRAM

Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity

64M x 16 Bit x 8 Banks DDR3(L) SDRAM

Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity

64M x 16 Bit x 8 Banks DDR3(L) SDRAM

Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity

64M x 16 Bit x 8 Banks DDR3(L) SDRAM

Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity

8M x 16 Bit x 8 Banks DDR3(L) SDRAM

文件：5.29147 Mbytes Page：147 Pages

DDR III SDRAM

16M x 16 Bit x 8 Banks DDR3(L) SDRAM

文件：4.60257 Mbytes Page：141 Pages

DDR3 SDRAM

32M x 8 Bit x 8 Banks DDR3(L) SDRAM

文件：4.57613 Mbytes Page：140 Pages

DDR3 SDRAM

32M x 16 Bit x 8 Banks DDR3(L) SDRAM

文件：8.277299 Mbytes Page：174 Pages

64M x 8 Bit x 8 Banks DDR3(L) SDRAM

文件：5.06177 Mbytes Page：174 Pages

4M x 16 Bit x 8 Banks DDR3(L) SDRAM

文件：6.671 Mbytes Page：172 Pages

64M x 16 Bit x 8 Banks DDR3(L) SDRAM

文件：8.21467 Mbytes Page：172 Pages