丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165Q；SN74LV165A-Q1 Automotive Parallel-Load 8-Bit Shift Registers

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: • 40°C to + 125°C, TA – Device HBM ESD Classifiaction Level 2 – Device CDM ESD Classifcation Level C6 • Available in wettable flank QFN (WBQB) package • 2 V to 5.5 V VCC operation • Maximum tpd of 10

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165A；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

丝印代码：LV165BEP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

丝印代码：LV165BEP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

丝印代码：LV165BEP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

丝印代码：LV165BEP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

丝印代码：LV165BEP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

文件：735.4 Kbytes Page：19 Pages

3A POWER OPERATIONAL AMPLIFIER

DESCRIPTION The L165 is a monolithic integrated circuit in Pen tawatt® package, intended for use as power operational amplifier in a wide range of applications, including servo amplifiers and power supplies. The high gain and high output power capability provide superiore performance wherever a

3A POWER OPERATIONAL AMPLIFIER

DESCRIPTION The L165 is a monolithic integrated circuit in Pen tawatt® package, intended for use as power operational amplifier in a wide range of applications, including servo amplifiers and power supplies. The high gain and high output power capability provide superiore performance wherever a

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Silicon MOS IC

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Description: The NTE165 is a silicon NPN transistor in a TO3 type package designed for use in color TV horizontal output applications. Features: • High Voltage • High Power • High Switching Speed • Good Stability Applications: • Consumer • Power Supply • Color TV