丝印代码：LV132；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

料位开关

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

丝印代码：LV132A；SN74LVC132A Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Operating range from 1.1V to 3.6V • 5.5V tolerant input pins • Supports standard pinouts • Latch-up performance exceeds 250mA per JESD 17 • ESD protection exceeds JESD 22 – 2000V Human-Body Model (A114-A) – 1000V Charged-Device Model (C101) 2 Applications Combining power g

丝印代码：LV132A；SN74LVC132A Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Operating range from 1.1V to 3.6V • 5.5V tolerant input pins • Supports standard pinouts • Latch-up performance exceeds 250mA per JESD 17 • ESD protection exceeds JESD 22 – 2000V Human-Body Model (A114-A) – 1000V Charged-Device Model (C101) 2 Applications • Combining power

SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

1 Features 1• 2-V to 5.5-V VCC Operation • Max t pd of 9 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Latch-Up Performance Exc

POWER TRANSISTORS(8.0A,60-100V,70W)

PLASTIC MEDIUM-POWER COMPLEMENTARY SILICON TRANSISTORS 8.0 AMPERE DARLINGTON COMPLEMENTARY SILICON POWER TRANSISTORS 60-100 VOLTS 70 WATTS

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DESCRIPTION The UPG137GV and UPG138GV are L-Band Single Pole Double Throw (SPDT) GaAs MMIC switches developed for digital cellular, PCS, and WLAN applications. These devices feature wide bandwidth, low insertion loss, and high P1dB. The UPG137GV operates on a +3 to +5 V control voltage, while the

L-BAND SPDT SWITCH

DESCRIPTION UPG133G is an L-Band SPDT (Single Pole Double Throw) GaAs FET switch which was developed for digital cellular or cordless telephone application. The device can operate from 100 MHz to 2.5 GHz, having the low insertion loss. It housed in an original 8 pin SSOP that is smaller than us

L-BAND SPDT SWITCH

DESCRIPTION µPG132G is an L-Band SPDT (Single Pole Double Throw) GaAs FET switch which was developed for digital cellular or cordless telephone application. The device can operate from 100 MHz to 2.5 GHz, having the low insertion loss. It housed in an original 8 pin SSOP that is smaller than us

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DESCRIPTION The µPG139GV is L-Band Double Pole, Double Throw (DPDT) switch developed for digital cellular or cordless telephone and PCS applications. This device feature low insertion loss, high handling power with low voltage operation. It is housed in a very small 8-pin plastic SSOP package ava