LMP202x Zero-Drift, Low-Noise, EMI-Hardened Amplifiers

1 Features 1(Typical Values, TA = 25°C, VS = 5 V) • Input Offset Voltage (Typical) −0.4 μV • Input Offset Voltage (Max) ±5 μV • Input Offset Voltage Drift (Typical) –0.004 μV/°C • Input Offset Voltage Drift (Max) ±0.02 μV/°C • Input Voltage Noise, AV = 1000 11 nV/√Hz • Open Loop Gain 160 dB

N-Channel, 20V, 0.89A, Small Signal MOSFET

Features z Trench Technology z Supper high density cell design z Excellent ON resistance z Extremely Low Threshold Voltage z Small package SOT-23/323 Applications z DC-DC converter circuit z Small Signal Switch z Load Switch z Level Shift

FIXED SIP DELAY LINE TR 1ns

FUNCTIONAL DESCRIPTION The 2020- and 2021-series devices are fixed, single-input, single-output, passive delay lines. The signal input (IN) is reproduced at the output (OUT), shifted by a time (TD) given by the device dash number. The characteristic impedance of the lines is nominally 50 ohms. Th

TOKEN RING MAGNETICS

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Snap Bushings

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PCB footprint

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