LMKDB1xxx PCIe Gen 1 to Gen 6 Ultra Low Jitter 1:20, 1:8, 1:4, 1:2, 2:4, 2:2 LP-HCSL Clock Buffer and Clock MUX

1 Features • LP-HCSL clock buffer and clock MUX that support: – PCIe Gen 1 to Gen 6 – CC (Common Clock) and IR (Independent Reference) PCIe architectures – Input clock with or without SSC • DB2000QL compliant: – All devices meet DB2000QL specifications – LMKDB1120 is pin-compatible to DB20

Customer Specification

Construction Diameters (In) 1) Component 1 4 X 1 COND a) Conductor 32 (7/40) AWG Tinned Copper 0.009 b) Insulation 0.010 Wall, Nom. PVC 0.029 (1) Color Code Alpha Wire Color Code D Cond Color Cond Color Cond Color 1 BLACK 3 WHITE 2 RED 4 GREEN 2) Cable Assembly 4 Components Cabled a) Twi

CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

8-Bit CODECs

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