LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

文件：3.42385 Mbytes Page：93 Pages

适用于通过 BAW 进行无线通信且采用 JESD204B 的超低抖动时钟同步器

LMK5B12212 1-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF) – 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF – 42fs typical/ 60fs maximum RMS jitter at 312.5MHz – 47fs typical/ 65fs maximum RMS jitt

LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

具有 JESD204B/C 和 BAW VCO 的三 DPLL、三 APLL、两输入和 16 输出网络同步器

Three DPLL, three APLL, two-input and 16-output network synchronizer with BAW VCO IEEE-1588 support

封装/外壳：64-VFQFN 裸露焊盘 包装：托盘 描述：IC POWER 集成电路（IC） 时钟发生器，PLL，频率合成器

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

文件：3.42385 Mbytes Page：93 Pages

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

文件：3.42385 Mbytes Page：93 Pages

封装/外壳：64-VFQFN 裸露焊盘 包装：托盘 描述：ULTRA-LOW JITTER CLOCK SYNCHRONI 集成电路（IC） 时钟发生器，PLL，频率合成器