LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1 Features 1• EP Features – Gold Bondwires – Temperature Range: –55 to +105 °C – Lead Finish SnPb • Maximum Distribution Frequency: 3.2 GHz • JESD204B Support • Ultra-Low RMS Jitter – 88-fs RMS Jitter (12 kHz to 20 MHz) – 91-fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at

具有集成式 2370 至 2630MHz VCO0 且符合 JESD204B 标准的超低噪声时钟抖动消除器

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.\n\nThe 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling • JEDEC JESD204B Support \n• 88 fs RMS Jitter (12 kHz to 20 MHz)\n• –162.5 dBc/Hz Noise Floor at 245.76 MHz\n• Up to 14 Differential Device Clocks from PLL2 \n• Maximum Clock Output Frequency 3.1 GHz\n• Up to 1 Buffered VCXO/Crystal Output from PLL1 \n• Dual Loop PLLatinum™ PLL Architecture\n• Up t;

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17702 Mbytes Page：102 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17326 Mbytes Page：102 Pages

LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1 Features 1• EP Features – Gold Bondwires – Temperature Range: –55 to +105 °C – Lead Finish SnPb • Maximum Distribution Frequency: 3.2 GHz • JESD204B Support • Ultra-Low RMS Jitter – 88-fs RMS Jitter (12 kHz to 20 MHz) – 91-fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at

温度范围为 -55°C 至 105°C 且符合 JESD204B 标准的超低噪声时钟抖动消除器

The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.\n\nThe 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. No • EP Features \n• Temperature Range: –55 to +105 °C\n• Maximum Distribution Frequency: 3.2 GHz\n• Ultra-Low RMS Jitter \n• 91-fs RMS Jitter (100 Hz to 20 MHz)\n• Up to 14 Differential Device Clocks From PLL2 \n• Maximum Clock Output Frequency 3.2 GHz\n• Up to 1 Buffered VCXO/Crystal Output From PL;

LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1 Features 1• EP Features – Gold Bondwires – Temperature Range: –55 to +105 °C – Lead Finish SnPb • Maximum Distribution Frequency: 3.2 GHz • JESD204B Support • Ultra-Low RMS Jitter – 88-fs RMS Jitter (12 kHz to 20 MHz) – 91-fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at

丝印代码：4828SNKDEP；LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1 Features 1• EP Features – Gold Bondwires – Temperature Range: –55 to +105 °C – Lead Finish SnPb • Maximum Distribution Frequency: 3.2 GHz • JESD204B Support • Ultra-Low RMS Jitter – 88-fs RMS Jitter (12 kHz to 20 MHz) – 91-fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at

丝印代码：4828SNKDEP；LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1 Features 1• EP Features – Gold Bondwires – Temperature Range: –55 to +105 °C – Lead Finish SnPb • Maximum Distribution Frequency: 3.2 GHz • JESD204B Support • Ultra-Low RMS Jitter – 88-fs RMS Jitter (12 kHz to 20 MHz) – 91-fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.44431 Mbytes Page：104 Pages

封装/外壳：64-WFQFN 裸露焊盘 包装：托盘 描述：IC CLOCK DUAL PLL 64-WQFN 集成电路（IC） 时钟发生器，PLL，频率合成器

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

封装/外壳：64-WFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLOCK DUAL PLL 64-WQFN 集成电路（IC） 时钟发生器，PLL，频率合成器

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

文件：2.23291 Mbytes Page：101 Pages

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

文件：2.79248 Mbytes Page：113 Pages

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17326 Mbytes Page：102 Pages

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17702 Mbytes Page：102 Pages

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17326 Mbytes Page：102 Pages

丝印代码：4828SNKDEP；Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17326 Mbytes Page：102 Pages

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17702 Mbytes Page：102 Pages

Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17702 Mbytes Page：102 Pages

丝印代码：4828SNKDEP；Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

文件：2.17326 Mbytes Page：102 Pages