功能：时钟调节器 包装：散装 描述：LMK04610EVM 开发板，套件，编程器 评估和演示板及套件

LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

文件：1.82179 Mbytes Page：124 Pages

LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

文件：1.82179 Mbytes Page：124 Pages