LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

Breake Away Header .025(0.64mm) Square Posts

[FOXCONN] Breake Away Header .025 (0.64mm) Square Posts

Breake Away Header .025(0.64mm) Square Posts

[FOXCONN] Breake Away Header .025 (0.64mm) Square Posts