| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
LMK04110 | LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 |   | |
LMK04110 | 具有集成式 1185MHz 至 1296MHz VCO 的抖动消除器：5 路输出用于 2VPEC/LVPEC | TI 德州仪器 | | |
LMK04110 | LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 文件：588.24 Kbytes Page：46 Pages | TI 德州仪器 | | |
LMK04110 | Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | |
LMK04110 | Clock Jitter Cleaner with Cascaded PLLs 文件：588.24 Kbytes Page：46 Pages | TI 德州仪器 | | |
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L | TI 德州仪器 | | ||
Clock Jitter Cleaner with Cascaded PLLs 文件：588.24 Kbytes Page：46 Pages | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 文件：588.24 Kbytes Page：46 Pages | TI 德州仪器 | | ||
Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 文件：588.24 Kbytes Page：46 Pages | TI 德州仪器 | | ||
Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | ||
封装/外壳：48-WFQFN 裸露焊盘 包装：卷带（TR） 描述：IC CLOCK COND W/PLL 48WQFN 集成电路（IC） 时钟发生器，PLL，频率合成器 | TI 德州仪器 | | ||
Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | ||
Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | ||
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs 文件：588.24 Kbytes Page：46 Pages | TI 德州仪器 | | ||
Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | ||
封装/外壳：48-WFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLOCK COND W/PLL 48WQFN 集成电路（IC） 时钟发生器，PLL，频率合成器 | TI 德州仪器 | | ||
Family Clock Jitter Cleaner 文件：1.20015 Mbytes Page：52 Pages | TI 德州仪器 | | ||
Breake Away Header .025(0.64mm) Square Posts [FOXCONN] Breake Away Header .025 (0.64mm) Square Posts | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
Breake Away Header .025(0.64mm) Square Posts [FOXCONN] Breake Away Header .025 (0.64mm) Square Posts | ETCList of Unclassifed Manufacturers 未分类制造商 | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI(德州仪器) |
24+ |
QFN48EP(7x7) |
1652 |
原装现货,免费供样,技术支持,原厂对接 |
|||
TI/德州仪器 |
24+ |
WQFN-48 |
9600 |
原装现货,优势供应,支持实单! |
|||
TI(德州仪器) |
24+ |
QFN48EP(7x7) |
1083 |
只做原装,提供一站式配单服务,代工代料。BOM配单 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10000 |
||||
Texas Instruments |
24+ |
48-WQFN(7x7) |
56200 |
一级代理/放心采购 |
|||
TI/德州仪器 |
25+ |
WQFN48 |
8880 |
原装认准芯泽盛世！ |
|||
TI/德州仪器 |
25+ |
48-WQFN |
65248 |
百分百原装现货 实单必成 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
9999 |
||||
TI |
22+ |
48WQFN |
9000 |
原厂渠道,现货配单 |
|||
NS |
23+ |
QFN |
13000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
LMK04110规格书下载地址
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2019-11-22
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