丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes Page：87 Pages

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes Page：87 Pages

封装/外壳：径向，Can 包装：托盘 描述：MAXCAP 220MF 5.5V 电容器 双电层电容器（EDLC），超级电容器

封装/外壳：径向，Can 包装：散装 描述：DOUBLE LAYER CAPACITOR 电容器 双电层电容器（EDLC），超级电容器