Features

• DisplayPort 1.4a Link Training Tunable PHY

Retimer (LTTPR) to support

− 4/2/1-Lane DP1.4a

(RBR/HBR/HBR2/HBR3)

• Power Supply Voltages

− 1.8 V for I/O, 1.2 V for Core

• DP1.4a Compliant Retimer

− Data rate 1.62 Gbps / 2.7 Gbps / 5.4

Gbps / 8.1 Gbps

− Transparent mode with proprietary link

training architecture

− Non-transparent mode support as

specified in DP1.4a standard

− AUX_CH transaction snooping

− DP1.4a Compliant Retimer DPCD

registers

− 8b/10b coding

− Pattern generator and Error Checker

− Down-spreading of link clock

− Error detection

− Adjustable TXEQ during the link training

through AUX_CH

− Adaptive equalizer with CTLE and DFE

− DFE + CTLE for HBR3 to compensate -

27dB insertion loss @4.05GHz

− CTLE for HBR2 / HBR / RBR

− Support of custom PHY configuration

through TWI

• Real time Eye Opening Monitor (EOM)

• TWI (Two Wire Interface) slave to configure

the integrated lane mapping and operation

mode

− Compatible with I2C master

− Support up to 4 unique TWI device ID

• Low Power Operation

− 460 mW for 4-lane HBR3 in typical

condition

− < 10mW in D3 mode

− < 1mW in low power mode

• ESD Specification

− 2kV HBM, ±500V CDM

• Package

− 46 Ex-VQFN (6.5 mm x 4.5 mm)

Applications

• Desktop PC / Notebook / Tablet

• Active cable

• Virtual Reality / Augmented Reality head

mount display

• DP1.4a monitor (8K monitor / Gaming

monitor)

• Video card / converter

• Video router / switch

• 4K / 8K UHD camera

• Video conferencing

• Digital signage

• Interactive display

1. Description

The MCDP6150 is a low power DisplayPort1.4a retimer targeted for high-end audio video applications. The

MCDP6150 supports 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps data rates. The following use cases are

supported.