Features

• Integrated USB Type-C DisplayPort alternate

mode lane switch to support

− Flip-ability of USB Type-C

− Simultaneous USB 3.2 x1 Enhanced

SuperSpeed (ESS) and 2 lane DP1.4a

− 4/2/1-Lane

DP1.4a(RBR/HBR/HBR2/HBR3)

• Power Supply Voltages

− 1.8 V for I/O, 1.2 V for core

• USB3.2 Appendix.E x1 Compliant Retimer

− 5 Gbps and 10 Gbps support

− Link training participation

− Spread-spectrum clocking as per USB 3.2

standard

− LFPS polling and processing

− LFPS Based PWM support

− Pass-Through / Local loopback

− Loopback BERT for USB 3.2 SS

− Lane polarity inversion

− BLR (Bit-Level Retimer) for SS mode

o Low latency data path

o Link layer snooping

▪ Link power management

support

− SRIS (Separate Reference clock

Independent SSC) for SSP mode

o 128b/132b coding

o Scrambler / De-scrambler

o Link power management support

o SKP OS handling / Elastic buffer

for USB for clock offset

compensation

o DC balance tracking / control

o Error correction

− Transmitter Emphasis

o 3-tap FIR TXEQ for SSP

o 2-tap TXEQ for SS

− Adaptive Receiver Equalization

o DFE + CTLE for SSP to support

-23dB insertion loss

compensation @5GHz

o CTLE for SS to support -20dB

insertion loss compensation

@2.5GHz

− Support of custom PHY configuration

through TWI (Two Wire Interface)

• DP1.4a Compliant Repeater

− Data rate 1.62 Gbps / 2.7 Gbps / 5.4

Gbps / 8.1 Gbps

− Transparent mode / Non-transparent

mode support

− AUX_CH transaction snooping

− DP1.4a Compliant Retimer DPCD

registers

− 8b/10b coding

− Pattern generator and Error Checker

− Down-spreading of link clock

− Error detection

− Adjustable TXEQ during the link training

through AUX_CH

− Adaptive equalizer with CTLE and DFE

o DFE + CTLE for HBR3 to

compensate -27dB insertion loss

@4.05GHz

o CTLE for HBR2 / HBR / RBR

− Support of custom PHY configuration

through TWI

• Real time Eye Opening Monitor (EOM)

• TWI slave to configure the integrated lane

mapping and operation mode

− Compatible with I2C master

− Support up to 4 unique TWI device ID

• Configuration pins for the integrated lane

switch and operation mode

• Low Power Operation

− 520 mW in USB 3.2 x1 SSP + Two lanes

of DisplayPort HBR3 operation with 1.2 V

and 1.8 V power supply

− 850 μW in standby mode

• ESD Specification

− 2kV HBM, ±500V CDM

• Package

− 46 Ex-VQFN (6.5 mm x 4.5 mm)

Applications

• Desktop PC / Notebook / Tablet /

Smartphone motherboard enabling USB

Type-C DP alternate mode

1. Description

The MCDP6000 is a low power USB 3.2 x1 and DisplayPort1.4a repeater device with an integrated USB

Type-C switch targeted for desktop / mobile PC motherboard-down application.

The USB 3.2 x1 retimer supports both SuperSpeed (SS) bit rate (5 Gbps), and SuperSpeedPlus (SSP) data

rate (10 Gbps). The USB 3.2 x1 retimer includes the link layer function and LTSSM and RTSSM to

participate in the link training. The MCDP6000 supports SS mode with a BLR (Bit-Level Retimer) and SSP

mode with a SRIS (Separate Reference clock Independent SSC). The MCDP6000 supports link power

management with Ux entry and exits in both SS and SSP modes. In addition, the MCDP6000 supports the

link state and link quality maintenance, compensates the clock offset between the downstream port and the

upstream port, detects errors, and corrects single symbol errors in framing order sets, single bit block header

errors, and single or double-bit SKP symbol errors in SSP mode. It also supports spread spectrum clocking

(SSC) to minimize EMI and the low frequency periodic signaling (LFPS). The transmitter employs 3-tap FIRbased

transmitter equalizer for SSP operation and fixed transmitter equalizer ranging from 3 dB to 4 dB for

SS operation. The receiver employs an adaptive Continuous Time Linear Equalizer (CTLE) and a Decision

Feedback Equalizer (DFE). Both the transmitter equalizer and the receiver equalizer are configurable

through the TWI register. Proper settings to comply with USB 3.2 electrical requirements are provided by default.