Description

The CD54AC163/3A and CD54ACT163/3A are synchronous presettable binary counters that utilize the Harris Advanced CMOS Logic technology. The CD54AC163/3A and CD54ACT163/3A are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock.

A LOW level on the Synchronous Parallel Enable input, SPE, disables the counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met).

The counters are reset with a LOW level on the Master Reset input, MR. The requirements for setup and hold time with respect to the clock must be met.

Two count enables, PE and TE, in each counter are provided for n-bit cascading. Reset action occurs regardless of the level of the SPE, PE and TE inputs.

The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be HIGH to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count, the terminal count (TC) output goes HIGH for one clock period. This TC pulse is used to enable the next cascaded stage.

The CD54AC163/3A and CD54ACT163/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).