位置:ICS8705BYT > ICS8705BYT详情

ICS8705BYT中文资料

厂家型号

ICS8705BYT

文件大小

293.42Kbytes

页面数量

17

功能描述

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

数据手册

下载地址一下载地址二

生产厂商

ICST

ICS8705BYT数据手册规格书PDF详情

GENERALDESCRIPTION

The ICS8705 is a highly versatile 1:8 Differen tial-to-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Per formance Clock Solutions from ICS. The ICS8705 has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The ICS8705 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz.

FEATURES

• 8 LVCMOS/LVTTL outputs, 7Ωtypical output impedance

• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs

• CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• CLK0 input accepts LVCMOS or LVTTL input levels

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration with configurable frequencies

• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Fully integrated PLL

• Cycle-to-cycle jitter: 45ps (maximum)

• Output skew: CLK0, 65ps (maximum)

CLK1, nCLK1, 55ps (maximum)

• Static Phase Offset: 25 ±125ps (maximum), CLK0

• Full 3.3V or 2.5V operating supply

• Lead-Free package available

• Industrial temperature information available upon request

更新时间:2025-10-6 11:00:00
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