ISPLSI2032A价格

参考价格:¥22.0084

型号:ISPLSI2032A-110LJ44 品牌:LATTICE SEMICONDUCTOR 备注:这里有ISPLSI2032A多少钱,2025年最近7天走势,今日出价,今日竞价,ISPLSI2032A批发/采购报价,ISPLSI2032A行情走势销售排行榜,ISPLSI2032A报价。
型号 功能描述 生产厂家 企业 LOGO 操作
ISPLSI2032A

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

Lattice

莱迪思

SPACERS , STANDOFFS

文件:297.49 Kbytes Page:1 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

3.3V In-System Programmable High Density SuperFAST??PLD

文件:179.32 Kbytes Page:14 Pages

Lattice

莱迪思

2.5V In-System Programmable SuperFAST??High Density PLD

文件:156.96 Kbytes Page:12 Pages

Lattice

莱迪思

ADSL LINE TRANSFORMER

文件:57.08 Kbytes Page:1 Pages

BOTHHAND

HIGH TEMPERATURE SERIES

文件:275.11 Kbytes Page:1 Pages

ASSUN

ISPLSI2032A产品属性

  • 类型

    描述

  • 型号

    ISPLSI2032A

  • 制造商

    LATTICE

  • 制造商全称

    Lattice Semiconductor

  • 功能描述

    In-System Programmable High Density PLD

更新时间:2025-11-24 20:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
LATTE/莱迪斯
24+
NA/
3419
原装现货,当天可交货,原型号开票
LATTICE/莱迪斯
25+
PLCC44
54648
百分百原装现货 实单必成 欢迎询价
LAT
24+
QFP
20000
全新原厂原装,进口正品现货,正规渠道可含税!!
LATTICE/莱迪斯
25+
PLCC
32360
LATTICE/莱迪斯全新特价ISPLSI2032A-80LJ44即刻询购立享优惠#长期有货
LATTICE
518
QFP44
216
一级代理,专注军工、汽车、医疗、工业、新能源、电力
LATTICE/莱迪斯
24+
TQFP44
7850
只做原装正品现货或订货假一赔十!
LATTICE
25+
LQFP44
18000
原厂直接发货进口原装
LATTICE
23+
BGAQFP
8659
原装公司现货!原装正品价格优势.
LATTICE
24+
PLCC44
17300
一级分销商,原装正品
LATTICE
25+
61
公司优势库存 热卖中!!

ISPLSI2032A数据表相关新闻