Low Noise, Low Power I2C Bus, 256 Taps

Low Noise, Low Power I2C® Bus, 256 Taps The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers a

Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

DIGITAL POTENTIOMETERS

文件：1.77378 Mbytes Page：8 Pages

Low Noise, Low Power I2C Bus, 256 Taps

丝印代码：ISL90840UA27Z；Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

丝印代码：ISL90840UI27；Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

丝印代码：ISL90840UI27Z；Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

丝印代码：ISL90840WA27Z；Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

丝印代码：ISL90840WI27；Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

丝印代码：ISL90840WI27Z；Quad Digitally Controlled Potentiometers (XDCP™)

Features • Four potentiometers in one package • 256 resistor taps - 0.4 resolution • I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability • Power-on preset to mid-scale (128 tap position) • Wiper resistance: 70 typical @ 3.3V • Standby current

Low Noise, Low Power I2C Bus, 256 Taps

Low Noise, Low Power I2C® Bus, 256 Taps The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers a

Low Noise, Low Power I2C Bus, 256 Taps

Low Noise, Low Power I2C® Bus, 256 Taps The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers a

Low Noise, Low Power I2C Bus, 256 Taps

Low Noise, Low Power I2C® Bus, 256 Taps The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers a

Low Noise, Low Power I2C Bus, 256 Taps

Low Noise, Low Power I2C® Bus, 256 Taps The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers a

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DGT POT 50KOHM 256TAP 20TSSOP 集成电路（IC） 数字电位计

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC DGT POT 50KOHM 256TAP 20TSSOP 集成电路（IC） 数字电位计

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

Quad Digitally Controlled Potentiometers (XDCP)

文件：1.09216 Mbytes Page：13 Pages

Distributed Hyperchannel Switch

Functional Description Real time multimedia applications require the transmission of mixed voice and data transmission into the same integrated network and transmission media. The network must simultaneously ensure that data (at N x 64 kbit/s) maintains time slot sequence integrity and provide co

Distributed Hyperchannel Switch

Functional Description Real time multimedia applications require the transmission of mixed voice and data transmission into the same integrated network and transmission media. The network must simultaneously ensure that data (at N x 64 kbit/s) maintains time slot sequence integrity and provide co

Distributed Hyperchannel Switch

Functional Description The MT90840 Distributed Hyperchannel Switch is a large switching, multiplexing, and rate-adapting device. The MT90840 bridges serial-bus telecom components, using the Zarlink ST-BUS or other industry-standard serial buses, onto a higher speed “backbone”. Mixed data, voice a

Distributed Hyperchannel Switch

Functional Description Real time multimedia applications require the transmission of mixed voice and data transmission into the same integrated network and transmission media. The network must simultaneously ensure that data (at N x 64 kbit/s) maintains time slot sequence integrity and provide co