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位置：首页 > IC中文资料 > IS61NVP409618B-200

型号 功能描述 生产厂家 企业 LOGO 操作
IS61NVP409618B-200B2I

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200B2L

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200B2LI

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200B3

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200B3I

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200B3L

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200B3LI

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200M3

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200M3I

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200M3L

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200M3LI

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200TQL

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200TQLI

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

IS61NVP409618B-200供应商更多...

更新时间：2025-12-12 13:54:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
深圳市科恒伟业电子有限公司
IS61NVP51236-200B3I-TR
ISSI
2450+
BGA
6540
只做原装正品假一赔十为客户做到零风险!!
询价
深圳市斌腾达科技有限公司
IS61NVP409618B-250B3L
ISSI, Integrated Silicon Solut
21+
48-VFBGA
5280
进口原装!长期供应!绝对优势价格(诚信经营
询价
深圳市威雅利发展有限公司
IS61NVP51236-200B3I
ISSI
0405+
BGA
23
一级代理,专注军工、汽车、医疗、工业、新能源、电力
询价
讯运(深圳/上海)电子有限公司
IS61NVP409618B-250B3L
ISSI(美国芯成)
2021+
TFBGA-165(13x15)
499
询价
深圳市冠亿通科技有限公司
IS61NVP409618B-250B3L-TR
ISSI,
25+
25000
原厂原包 深圳现货 主打品牌 假一赔百 可开票!
询价
深圳市纳艾斯科技有限公司
IS61NVP51236-200B3I
ISSI
24+
BGA
80000
只做自己库存 全新原装进口正品假一赔百 可开13%增
询价
贸泽芯城（深圳）电子科技有限公司
IS61NVP51218A-200B3I
ISSI
23+
BGA165
3000
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
询价
深圳市高捷芯城科技有限公司
IS61NVP409618B-250B3L
ISSI(美国芯成)
24+
TFBGA165(13x15)
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
深圳市安富世纪电子有限公司
IS61NVP409618B-250B3L
ISSI, Integrated Silicon Solu
23+
-
7300
专注配单,只做原装进口现货
询价
艾睿（深圳）半导体有限公司
IS61NVP409618B-250B3L
ISSI(美国芯成)
2447
TFBGA-165(13x15)
315000
144个/托盘一级代理专营品牌!原装正品,优势现货,长
询价

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