型号 功能描述 生产厂家 企业 LOGO 操作
IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K

ISSI

矽成半导体

更新时间:2025-12-24 17:57:00
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