型号 功能描述 生产厂家 企业 LOGO 操作

256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MO

ISSI

矽成半导体

256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MO

ISSI

矽成半导体

256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MO

ISSI

矽成半导体

256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

文件:251.56 Kbytes Page:35 Pages

ISSI

矽成半导体

256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

文件:251.56 Kbytes Page:35 Pages

ISSI

矽成半导体

更新时间:2025-12-11 19:09:01
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