PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 wor

128K x 32 pipeline no wait state bus sram