型号 功能描述 生产厂家 企业 LOGO 操作
IS61NLP25636B-200B2L

256K x 36 and 512K x 18 9Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

ISSI

矽成半导体

更新时间:2026-2-5 10:03:00
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只做原装正品现货或订货假一赔十!
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ISSI/芯成
24+
QFP
60000
ISSI
23+
1639
7000

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