封装/外壳：165-TBGA 包装：卷带（TR） 描述：IC SRAM 18MBIT PARALLEL 165TFBGA 集成电路（IC） 存储器

256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo

256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo

256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi