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IS61NLP10价格
参考价格：￥111.3304
型号：IS61NLP102418-200TQLI 品牌：ISSI 备注：这里有IS61NLP10多少钱，2026年最近7天走势，今日出价，今日竞价，IS61NLP10批发/采购报价，IS61NLP10行情走势销售排行榜，IS61NLP10报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 |   | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M wo | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
1Mb x 36 and 2Mb x 18 STATE BUS SRAM DESCRIPTION The 36 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricate | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | | ||
36Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi | ISSI 矽成半导体 | |
IS61NLP10产品属性
- 类型
描述
- 型号
IS61NLP10
- 功能描述
静态随机存取存储器 18Mb,No-Wait/Pipeline,Sync,1Mb x 18,200Mhz,3.3v/2.5v - I/O,165 Ball BGA
- RoHS
否
- 制造商
Cypress Semiconductor
- 存储容量
16 Mbit
- 组织
1 M x 16
- 访问时间
55 ns
- 电源电压-最大
3.6 V
- 电源电压-最小
2.2 V
- 最大工作电流
22 uA
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 安装风格
SMD/SMT
- 封装/箱体
TSOP-48
- 封装
Tray
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ISSI |
21+ |
QFP |
10000 |
原装现货假一罚十 |
|||
ISSI |
24+ |
SOP |
42500 |
专营ISSI进口原装现货可开17增值税票 |
|||
ISSI/芯成 |
24+ |
QFP |
24000 |
只做原装进口现货 |
|||
ISSI |
25+ |
TSOP |
15000 |
原厂原装,价格优势 |
|||
ISSI |
20+ |
100TQFP |
500 |
样品可出,优势库存欢迎实单 |
|||
ISSI |
24+ |
65200 |
|||||
ISSI |
2023+ |
QFP |
8635 |
一级代理优势现货,全新正品直营店 |
|||
ISSI |
24+ |
QFP100 |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
ISSI |
23+ |
NA |
1 |
专业电子元器件供应链正迈科技特价代理特价，原装元器件供应，支持开发样品 |
|||
ISSI |
2447 |
QFP |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
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- IS607X
- IS607
- IS6051
- IS604X
- IS604
- IS6030
- IS6015X
- IS6015
- IS6010X
- IS6010
- IS6005X
- IS6005
IS61NLP10数据表相关新闻
IS61C5128AS-25TLI
进口代理
2022-8-10IS61LV25616AL-10T现货热卖！！！！
IS61LV25616AL-10T现货热卖！！！！
2021-7-7IS61SF12832-8.5TQ
产品属性 属性值 搜索类似 制造商: ISSI 产品种类: 静态随机存取存储器 存储容量: 4 Mbit 访问时间: 8.5 ns 最大时钟频率: 90 MHz 电源电压-最大: 3.63 V 电源电压-最小: 3.135 V 电源电流—最大值: 230 mA 最小工作温度: 0 C 最大工作温度: + 70 C 安装风格: SMD/SMT 封装 / 箱体: TQFP-100 数
2020-7-13IS61SF12832-8.5TQ
原装正品 热卖 假一赔十
2020-7-13IS61LV256AH-15JI，IS61LV256AH-10T，IS61LV256AH-10TI，IS61LV256AH-12J，IS61LV2568L-12TI，IS61LV2568L-10TLI，IS61LV2568L-10K，IS61LV2568-12T，IS61LV2568-12K，IS61LV2568-15T
IS61LV256AH-15JI，IS61LV256AH-10T，IS61LV256AH-10TI，IS61LV256AH-12J，IS61LV2568L-12TI，IS61LV2568L-10TLI，IS61LV2568L-10K，IS61LV2568-12T，IS61LV2568-12K，IS61LV2568-15T
2020-1-1IS62C256AL-45TLI进口原装假一赔十
瀚佳科技(深圳）有限公司： 专业销售集成电路IC.单片机.内存闪存.二三级管模块等电子元器件。
2018-12-30
DdatasheetPDF页码索引
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