型号 功能描述 生产厂家 企业 LOGO 操作

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

ISSI

矽成半导体

封装/外壳:100-LQFP 包装:托盘 描述:IC SRAM 36MBIT PARALLEL 100LQFP 集成电路(IC) 存储器

ETC

知名厂家

封装/外壳:100-LQFP 包装:卷带(TR) 描述:IC SRAM 36MBIT PARALLEL 100LQFP 集成电路(IC) 存储器

ETC

知名厂家

更新时间:2025-12-14 15:09:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ISSI
1706+
?
8450
只做原装进口,假一罚十
ISSI
2447
TQFP100
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
ISSI(美国芯成)
25+
LQFP-100(14x20)
500000
源自原厂成本,高价回收工厂呆滞
ISSI
23+
BGA
7000
ISSI,
25+
25000
原厂原包 深圳现货 主打品牌 假一赔百 可开票!
ISSI
1041+
BGA119
1680
一级代理,专注军工、汽车、医疗、工业、新能源、电力
ISSI, Integrated Silicon Solut
21+
54-VFBGA
5280
进口原装!长期供应!绝对优势价格(诚信经营
ISSI
23+
TQFP100
10800
原厂授权一级代理,专业海外优势订货,价格优势、品种
ISSI
23+
BGA
50000
全新原装正品现货,支持订货
ISSI
25+
电联咨询
7800
公司现货,提供拆样技术支持

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