型号 功能描述 生产厂家 企业 LOGO 操作

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and networking applications. The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD1

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and • control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs

ISSI

矽成半导体

Synchronous SRAM

ISSI

矽成半导体

封装/外壳:165-TBGA 包装:托盘 描述:IC SRAM 18MBIT PARALLEL 165PBGA 集成电路(IC) 存储器

ETC

知名厂家

封装/外壳:165-TBGA 包装:卷带(TR) 描述:IC SRAM 18MBIT PARALLEL 165PBGA 集成电路(IC) 存储器

ETC

知名厂家

Synchronous SRAM

ISSI

矽成半导体

IS61LPD51236产品属性

  • 类型

    描述

  • 型号

    IS61LPD51236

  • 功能描述

    静态随机存取存储器 18Mb 512Kx36 200MHz Sync 静态随机存取存储器 3.3v

  • RoHS

  • 制造商

    Cypress Semiconductor

  • 存储容量

    16 Mbit

  • 组织

    1 M x 16

  • 访问时间

    55 ns

  • 电源电压-最大

    3.6 V

  • 电源电压-最小

    2.2 V

  • 最大工作电流

    22 uA

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    TSOP-48

  • 封装

    Tray

更新时间:2025-12-15 18:29:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ISSI
21+
TQFP100
1975
ISSI
24+
SMD
12000
专营ISSI进口原装正品假一赔十可開17增值稅票
ISSI Integrated Silicon Solut
25+
165-TBGA
9350
独立分销商 公司只做原装 诚心经营 免费试样正品保证
ISSI, Integrated Silicon Solut
21+
BGA
1000
进口原装!长期供应!绝对优势价格(诚信经营
ISSI
23+
100-TQFP(14x20)
9550
专业分销产品!原装正品!价格优势!
ISSI
22+
BGA
5000
全新原装现货!自家库存!
ISSI Integrated Silicon Soluti
22+
100TQFP (14x20)
9000
原厂渠道,现货配单
ISSI
1701+
?
8450
只做原装进口,假一罚十
ISSI, Integrated Silicon Solut
24+
165-TFBGA(13x15)
56200
一级代理/放心采购
ISSI, Integrated Silicon Solu
23+
165-TFBGA13x15
7300
专注配单,只做原装进口现货

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