型号 功能描述 生产厂家 企业 LOGO 操作
IS61LF51236B-7.5B2L

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

ISSI

矽成半导体

更新时间:2025-11-23 15:01:00
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