IS43R86400D价格

参考价格:¥44.0956

型号:IS43R86400D-5BL 品牌:ISSI 备注:这里有IS43R86400D多少钱,2025年最近7天走势,今日出价,今日竞价,IS43R86400D批发/采购报价,IS43R86400D行情走势销售排行榜,IS43R86400D报价。
型号 功能描述 生产厂家 企业 LOGO 操作
IS43R86400D

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

IS43R86400D

DDR SDRAM

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-6) • VDD and VDDQ: 2.6V ± 0.1V (-5) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS

ISSI

矽成半导体

封装/外壳:60-TFBGA 包装:托盘 描述:IC DRAM 512MBIT PARALLEL 60TFBGA 集成电路(IC) 存储器

ETC

知名厂家

封装/外壳:60-TFBGA 包装:卷带(TR) 描述:IC DRAM 512MBIT PARALLEL 60TFBGA 集成电路(IC) 存储器

ETC

知名厂家

更新时间:2025-12-18 12:01:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ISSI
24+
NA
57254
特价原装假一送奔驰
ISSI
2023+
60TFBGA
2090
原厂全新正品旗舰店优势现货
ISSI
23+
BGA
8650
受权代理!全新原装现货特价热卖!
ISSI/矽成
1113
DDR1SDRAM/64MX8DDR1/BGA6
126
原装香港现货真实库存。低价
ISSI
24+
TSOP66
9600
原装现货,优势供应,支持实单!
ISSI/芯成
2025+
TSOP-66
5000
原装进口价格优 请找坤融电子!
ISSI
23+
TSOP66
4776
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
ISSI
三年内
1983
只做原装正品
ISSI
1809+
60TFBGA
2090
一级代理,专注军工、汽车、医疗、工业、新能源、电力
ISSI, Integrated Silicon Solu
23+
66-TSOP II
7300
专注配单,只做原装进口现货

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