4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

封装/外壳：90-TFBGA 包装：托盘 描述：IC DRAM 128MBIT PARALLEL 90TFBGA 集成电路（IC） 存储器

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

封装/外壳：90-TFBGA 包装：管件 描述：IC DRAM 128MBIT PARALLEL 90TFBGA 集成电路（IC） 存储器

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync