封装/外壳：86-TFSOP（0.400"，10.16mm 宽） 包装：托盘 描述：IC DRAM 128MBIT PAR 86TSOP II 集成电路（IC） 存储器

4Meg x 32 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully s

4Meg x 32 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully s

4Meg x 32 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully s

4Meg x 32 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully s

4Meg x 32 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully s