封装/外壳：54-TSOP（0.400"，10.16mm 宽） 包装：卷带（TR） 描述：IC DRAM 128MBIT PAR 54TSOP II 集成电路（IC） 存储器

16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signal

16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signal

16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signal

16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signal

16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signal