1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The IN74HC154A is identical inpinouttothe LS/ALS154. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device, when enabled, selects one of 16

1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The IN74HC154A is identical inpinouttothe LS/ALS154. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device, when enabled, selects one of 16

1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The IN74HC154A is identical inpinouttothe LS/ALS154. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device, when enabled, selects one of 16

1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

4-16 Decoder/Demultiplexer (3-State)

4-to-16 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT154 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 16-line demultiplexing capability • Decodes 4 binary-coded inputs into one of 16

4-to-16 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT154 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 16-line demultiplexing capability • Decodes 4 binary-coded inputs into one of 16

4-to-16 line decoder/demultiplexer

4-to-16 line decoder/demultiplexer

Dual 1-of-16 Decoder / Demultiplexer in bare die form

Description The 74HC154 is fabricated using a 2.5μm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. The device consists of x4 active-high binary address inputs, x16 active-low outputs & x2 active-low chip-selects. The x2 active-low