Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

Octal Transparent Latch with 3-STATE Outputs

General Description The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Out

Octal Transparent Latch with 3-STATE Outputs

General Description The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Out

Octal Transparent Latch with 3?뭆tate Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t