Zero Delay, Low Skew Buffer

Description The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on ICS’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLOCK ZDB 1:4 160MHZ 8SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Zero Delay, Low Skew Buffer

Description The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on ICS’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLOCK ZDB 1:4 160MHZ 8SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

ZERO DELAY, LOW SKEW BUFFER

文件：168.91 Kbytes Page：7 Pages

Complete 12-Bit A/D Converter

PRODUCT DESCRIPTION The AD574A is a complete 12-bit successive-approximation analog-to-digital converter with 3-state output buffer circuitry for direct interface to an 8- or 16-bit microprocessor bus. A high precision voltage reference and clock are included on-chip, and the circuit guarantees f

Stratum 3 TCXO/TCVCXO

文件：194.95 Kbytes Page：5 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：332.9 Kbytes Page：17 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：332.9 Kbytes Page：17 Pages

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：529.08 Kbytes Page：16 Pages