PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

PLL Clock Divider

丝印代码：ICS54110AIL；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

丝印代码：ICS54110AIL；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

丝印代码：ICS54110AIL；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

丝印代码：ICS54110AIL；2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

NPN 9 GHz wideband transistor

DESCRIPTION NPN silicon planar epitaxial transistor, intended for wideband applications in the GHz range, such as analog and digital cellular telephones, cordless telephones (CT1, CT2, DECT, etc.), radar detectors, satellite TV tuners (SATV), MATV/CATV amplifiers and repeater amplifiers in fibr

262,214-Word x 12-Bit Field Memory

DESCRIPTION The OKI MSM5412222 is a high performance 3-Mbit, 256K · 12-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM5412222 is a FRAM for wide or low end use in gener

EARTH LEAKAGE CURRENT DETECTOR

DESCRIPTION The M54122L is a semiconductor integrated circuit with amplifier for a high-speed earth leakage circuit breaker. FEATURES ● Suitable for JIS C 8371 ● Good temperature characteristics of input sensitivity current ● High input sensitivity (VT = 13.5mV Typ.) ● Low exte

Dual 4-Line to 1-Line Data Selectors/Multiplexers

文件：120.48 Kbytes Page：6 Pages

Dual Retriggerable One-Shot with Clear and Complementary Outputs

文件：130.82 Kbytes Page：6 Pages