丝印代码：ICS507M-01LF；PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

丝印代码：ICS507M-01LF；PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

丝印代码：ICS507M-01；PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol