31.0 dB, DC-4GHz, 5 Bit Parallel Digital Attenuator

文件：91.56 Kbytes Page：7 Pages

31.0 dB, DC-4GHz, 5 Bit Parallel Digital Attenuator

文件：91.56 Kbytes Page：7 Pages

31.0 dB, DC-4GHz, 5 Bit Parallel Digital Attenuator

包装：盒 描述：BOARD EVALUATION FOR HRF-AT4520 开发板，套件，编程器 射频评估和开发套件，开发板

31.0 dB, DC-4GHz, 5 Bit Parallel Digital Attenuator

文件：91.56 Kbytes Page：7 Pages

封装/外壳：24-VQFN 包装：托盘 描述：RF ATTENUATOR 31DB 50OHM 24VQFN RF/IF，射频/中频和 RFID 衰减器

31.0 dB, DC-4GHz, 5 Bit Parallel Digital Attenuator

文件：91.56 Kbytes Page：7 Pages

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou