Quadruple D-type flip-flop

DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans

CMOS Quad D - Type Flip-Flop

Features: 100% tested for quiescent current at20v Maximum input current of 1 uA at 18 V over full package- temperature range; 100.nA at 18V and 25°C | Noise margin (full package- temperature range) = 1VatVoo=5V 2VatVop=10V 25VatVoo=15V 5-V, 10-V, and 15-V parametric ratings Meets

CMOS QUAD D-TYPE FLIP-FLOP

文件：544.46 Kbytes Page：14 Pages

CMOS Quad D-type Flip-Flop

文件：940.2 Kbytes Page：18 Pages

Hex,Quad D Flip-Flop

文件：135.25 Kbytes Page：6 Pages

Hex D Flip-Flop

文件：135.26 Kbytes Page：6 Pages

Hex,Quad D Flip-Flop

Hex D Flip-Flop

Quadruple D-type Flip Flop

Quad D-type flip-flop Complies with JEDEC standard JESD 13-B

Quad D-type flip-flop Standardized symmetrical output characteristics

Quadruple D-type flip-flop

Quadruple D-type flip-flop

Quad D-type flip-flop Complies with JEDEC standard JESD 13-B

Quad Type D Flip−Flop

Quad Type D Flip-Flop

C2MOS DIGITAL INTEGRATED CIRCUIT QUAD D-TYPE FLIP-FLOP