HEF40175B价格
参考价格：￥3.4054
型号：HEF40175BP,652 品牌：NXP 备注：这里有HEF40175B多少钱，2026年最近7天走势，今日出价，今日竞价，HEF40175B批发/采购报价，HEF40175B行情走势销售排行榜，HEF40175B报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
HEF40175B | Quadruple D-type flip-flop DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans | PHILIPS 飞利浦 |   | |
HEF40175B | Quad D-type flip-flop 1. General description The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requireme | NEXPERIA 安世 | | |
HEF40175B | Quadruple D-type flip-flop | ETC 知名厂家 | ETC | |
HEF40175B | Quad D-type flip-flop Complies with JEDEC standard JESD 13-B | ETC 知名厂家 | ETC | |
HEF40175B | Quad D-type flip-flop Standardized symmetrical output characteristics | ETC 知名厂家 | ETC | |
Quadruple D-type flip-flop DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans | PHILIPS 飞利浦 | | ||
Quadruple D-type flip-flop DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans | PHILIPS 飞利浦 | | ||
Quadruple D-type flip-flop DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans | PHILIPS 飞利浦 | | ||
Quadruple D-type flip-flop DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans | PHILIPS 飞利浦 | | ||
Quadruple D-type flip-flop DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop 1. General description The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requireme | NEXPERIA 安世 | | ||
Quad D-type flip-flop The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 o • Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from –40 ℃ to +125 ℃\n• Complies with JEDEC standard JESD 13-B; | NEXPERIA 安世 | | ||
Quad D-type flip-flop 1. General description The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requireme | NEXPERIA 安世 | | ||
Quad D-type flip-flop The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 o • Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from –40 ℃ to +125 ℃\n• Complies with JEDEC standard JESD 13-B; | NEXPERIA 安世 | | ||
Quad D-type flip-flop Standardized symmetrical output characteristics | ETC 知名厂家 | ETC | | |
Quad D-type flip-flop Complies with JEDEC standard JESD 13-B | ETC 知名厂家 | ETC | | |
Quad D-type flip-flop Complies with JEDEC standard JESD 13-B | ETC 知名厂家 | ETC | | |
Quad D-type flip-flop Complies with JEDEC standard JESD 13-B | ETC 知名厂家 | ETC | | |
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 4BIT 16SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 4BIT 16SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Quad D-type flip-flop Complies with JEDEC standard JESD 13-B | ETC 知名厂家 | ETC | | |
Hex,Quad D Flip-Flop 文件：135.25 Kbytes Page：6 Pages | NSC 国半 | | ||
Hex,Quad D Flip-Flop 文件：135.25 Kbytes Page：6 Pages | NSC 国半 | | ||
Hex,Quad D Flip-Flop 文件：135.25 Kbytes Page：6 Pages | NSC 国半 | | ||
Hex,Quad D Flip-Flop 文件：135.25 Kbytes Page：6 Pages | NSC 国半 | | ||
Hex,Quad D Flip-Flop 文件：135.25 Kbytes Page：6 Pages | NSC 国半 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Hex,Quad D Flip-Flop | NSC 国半 | NSC | | |
Hex D Flip-Flop | NSC 国半 | NSC | | |
Quadruple D-type Flip Flop | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Quad Type D Flip-Flop | ONSEMI 安森美半导体 | ONSEMI | | |
Quad Type D Flip−Flop | ONSEMI 安森美半导体 | ONSEMI | | |
C2MOS DIGITAL INTEGRATED CIRCUIT QUAD D-TYPE FLIP-FLOP | ICSI | ICSI | |
HEF40175B产品属性
- 类型
描述
- VCC (V)：
3.0 - 15
- Logic switching levels：
CMOS
- Output drive capability (mA)：
± 2.4
- tpd (ns)：
25
- fmax (MHz)：
45
- Power dissipation considerations：
low
- Tamb (°C)：
-40~85
- Rth(j-a) (K/W)：
81
- Ψth(j-top) (K/W)：
4.7
- Rth(j-c) (K/W)：
39.8
- Package name：
SO16
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
恩XP |
25+ |
SO-16 |
30000 |
原装正品公司现货,假一赔十! |
|||
恩XP |
23+ |
9865 |
原装正品,假一赔十 |
||||
恩XP |
22+ |
16TSSOP |
9000 |
原厂渠道,现货配单 |
|||
恩XP |
23+ |
SOP16 |
8000 |
原装正品,假一罚十 |
|||
PHI |
SOP |
68500 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
PHI |
1994 |
SOP |
516 |
原装现货海量库存欢迎咨询 |
|||
恩XP |
21+ |
SO-16 |
8080 |
只做原装,质量保证 |
|||
恩XP |
2023+ |
SOP16 |
1855 |
十五年行业诚信经营,专注全新正品 |
|||
恩XP |
24+ |
SOP16 |
9600 |
原装现货,优势供应,支持实单! |
|||
Nexperia(安世) |
25+ |
SO16 |
2181 |
原装现货,免费供样,技术支持,原厂对接 |
HEF40175B规格书下载地址
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