Octal Bus Transceivers (with 3-state outputs)

Description Both the HD74HCT640 and the HD74HCT643 have one active low enable input (G), and a direction control (DIR). When the DIR input is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from B to A. The HD74HCT640 transfers inverted data from one bus to the o

Octal Bus Transceivers (with inverted 3-state outputs) Octal Bus Transceivers (with 3-state outputs)

Features • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility • High Speed Operation: tpd (A to B) = 14.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 4.5 to 5.5 V • Low Input Current: 1 μA max • Low Quiescent Su

Octal Bus Transceivers (with 3-state outputs)

Octal Bus Transceivers (with inverted 3-state outputs) Octal Bus Transceivers (with 3-state outputs)

Features • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility • High Speed Operation: tpd (A to B) = 14.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 4.5 to 5.5 V • Low Input Current: 1 μA max • Low Quiescent Su

Octal Bus Transceivers (with inverted 3-state outputs) Octal Bus Transceivers (with 3-state outputs)

Features • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility • High Speed Operation: tpd (A to B) = 14.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 4.5 to 5.5 V • Low Input Current: 1 μA max • Low Quiescent Su

Octal Bus Transceivers (with inverted 3-state outputs) Octal Bus Transceivers (with 3-state outputs)

Features • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility • High Speed Operation: tpd (A to B) = 14.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 4.5 to 5.5 V • Low Input Current: 1 μA max • Low Quiescent Su

Octal bus transceiver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send

Octal bus transceiver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send

Octal bus transceiver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send

Octal bus transceiver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send

Octal bus transceiver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send