Octal D-type Transparent Latches (with 3-state outputs)/Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again

Octal D-type Transparent Latches (with 3-state outputs)

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Octal D-type transparent latch; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT533 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state inverting outputs for bus oriented applications • Common 3-state outp

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING

DESCRIPTION The M54/74HC373/533 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. The application designer has a choise of

Octal 3-State Inverting Transparent Latch(High-Performance Silicon-Gate CMOS)

Octal 3-State Inverting Transparent Latch High-Performance Silicon-Gate CMOS The SL74HC533 is identical in pinout to the LS/ALS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to

High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：50.92 Kbytes Page：9 Pages