Octal D-type Transparent Latches (with 3-state outputs)/Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again

Octal D-type Transparent Latches (with 3-state outputs)

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Octal D-type transparent latch; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT533 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state inverting outputs for bus oriented applications • Common 3-state outp

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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