BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 outpt drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the 7

BCD-to-Seven Segment Latch/Decoder/Driver

Features • High Speed Operation: tpd (A, B, C, D to a – g) = 33 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 μA max • Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C) • Ordering Informatio

BCD-to-Seven Segment Latch/Decoder/Driver

BCD-to-Seven Segment Latch/Decoder/Driver

Features • High Speed Operation: tpd (A, B, C, D to a – g) = 33 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 μA max • Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C) • Ordering Informatio

BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the

BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the

BCD-to-Seven Segment Latch/Decoder/Driver

Features • High Speed Operation: tpd (A, B, C, D to a – g) = 33 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 μA max • Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C) • Ordering Informatio

BCD-to-Seven Segment Latch/Decoder/Driver

Features • High Speed Operation: tpd (A, B, C, D to a – g) = 33 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 μA max • Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C) • Ordering Informatio

BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the

BCD-to-Seven Segment Latch/Decoder/Driver

BCD to 7-segment latch/decoder/driver for LCDs

GENERAL DESCRIPTION The 74HC/HCT4543 are high-speed Si-gate CMOS devices and are pin compatible with “4543” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Latch storage of inputs • Blanking inputs • Output capability: non-standard

HIGH-SPEED CMOS LOGIC(BCD-TO7 SEGMENT LATCH/DECODER/DRIVER FOR LCDS)

文件：198.17 Kbytes Page：7 Pages

High-Speed CMOS Logic BCD to 7-Segment Latch/Decoder/Driver for LCDs

文件：178.23 Kbytes Page：10 Pages

BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER

文件：256.89 Kbytes Page：12 Pages