Quad. Bus Transceivers (with noninverted 3-state outputs)

Description The HD74HC243 is a noninverting buffer. Each device has one active high enable (GBA), and one active low enable (GAB). GBA enables the A output and GAB enables the B outputs. The device does not have schmitt trigger inputs. Features • High Speed Operation: tpd = 10 ns typ (CL =

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil