Parallel-load 8-bit Shift Register

This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.

Parallel-load 8-bit Shift Register

Description This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Features • High Speed Operation: tpd

Parallel-load 8-bit Shift Register

Parallel-load 8-bit Shift Register

Parallel-load 8-bit Shift Register

Description This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Features • High Speed Operation: tpd

Parallel-load 8-bit Shift Register

Description This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Features • High Speed Operation: tpd

Parallel-load 8-bit Shift Register

文件：115.19 Kbytes Page：10 Pages

Parallel-load 8-bit Shift Register

文件：115.19 Kbytes Page：10 Pages

General-Purpose Logics-HD/RD74HC Series

Parallel-load 8-bit Shift Register

文件：115.19 Kbytes Page：10 Pages

8-bit parallel-in/serial out shift register

1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8-bit parallel-in/serial out shift register

8-bit parallel-in/serial out shift register

1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D

8-bit parallel-in/serial out shift register