Hex Schmitt-trigger Inverters

Features • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Hex Inverters

Features • High Speed Operation: tpd= 10.5 ns typ (CL= 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC= 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC(static) = 1 µA max (Ta = 25°C)

Hex Schmitt-trigger Inverters

Standard IC>General-Purpose Logics>HD74HC Series

10-to-4-line Priority Encoder

Description The HD74HC147 features priority encoding of the inputs to ensure that only the highest order data line is encoded. Nine input lines are encoded to a four line BCD output. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are a

10-to-4-line Priority Encoder

The HD74HC147 features priority encoding of the inputs to ensure that only the highest order data line is encoded. Nine input lines are encoded to a four line BCD output. The implied decimal zero codition requires no input condition as zero is encoded when all nine data lines are at a high logic l

10-to-4-line Priority Encoder

Description The HD74HC147 features priority encoding of the inputs to ensure that only the highest order data line is encoded. Nine input lines are encoded to a four line BCD output. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are a

10-to-4-line Priority Encoder

Description The HD74HC147 features priority encoding of the inputs to ensure that only the highest order data line is encoded. Nine input lines are encoded to a four line BCD output. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are a

8-to-3-line Octal Priority Encoder

Description The HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry.The data inputs and outputs are active at the low logic level. Fe

8-to-3-line Octal Priority Encoder

Description HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level. Featu

8-to-3-line Octal Priority Encoder

Description HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level. Featu

8-to-3-line Octal Priority Encoder

Description HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level. Featu

8-to-8-line Priority Encoder

Description The HD74HC149 is priority encoder which has 8 input lines (0 - 7) and 8 output lies (Y0 - Y7). It is the logical combination of a HD74HC148 8-3 line priority encoder driving a HD74HC138 3-8 line decoder. Only one request output can be low at a time. The output that is low is depende

8-to-8-line Priority Encoder

Description The HD74HC149 is priority encoder which has 8 input lines (0 - 7) and 8 output lies (Y0 - Y7). It is the logical combination of a HD74HC148 8-3 line priority encoder driving a HD74HC138 3-8 line decoder. Only one request output can be low at a time. The output that is low is depende

Hex Schmitt-trigger Inverters

Features • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Hex Inverters

Features • High Speed Operation: tpd= 10.5 ns typ (CL= 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC= 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC(static) = 1 µA max (Ta = 25°C)

Hex Inverters

Features • High Speed Operation: tpd= 10.5 ns typ (CL= 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC= 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC(static) = 1 µA max (Ta = 25°C)

Hex Inverters

Features • High Speed Operation: tpd= 10.5 ns typ (CL= 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC= 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC(static) = 1 µA max (Ta = 25°C)

Hex Inverters

Features • High Speed Operation: tpd= 10.5 ns typ (CL= 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC= 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC(static) = 1 µA max (Ta = 25°C)

HD74HC147 / 10-to-4-line Priority Encoder

High-Speed Cmos Logic Hex Inverting Schmitt Trigger

High-Speed Cmos Logic Hex Inverting Schmitt Trigger The 74HC14 is useful to “square up” slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the 74HC14 finds applications in noisy environments. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Vol

Hex inverting Schmitt trigger

DESCRIPTION The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of tr

Hex Schmitt?뭈rigger Inverter High?뭁erformance Silicon?묰ate CMOS

The 74HC14 is identical in pinout to the LS14, LS04 and the HC04. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC14 is useful to “square up” slow input rise and fall times. Due to hysteresis voltage of the Schmitt t

Hex inverting Schmitt trigger

DESCRIPTION The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of tr

Hex inverting Schmitt trigger