Octal D-Type Flip-Flops with 3-State Output

Description The HD74AC374/HD74ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Features • Buffered Positive E

OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input

OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input

OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input

OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input

OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input