Octal Transparent Latch with 3-State Output

Description Diagram The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. Features • Eight Latches in a Single Package • 3-State Outputs for Bus Interfacing • Outputs Source/Sink 24 mA • HD74AC373 has TTL-Compatible Inputs

Octal Transparent Latch with 3-State Output

Description The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when th

Octal Transparent Latch with 3-State Output

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Octal Transparent Latch with 3-State Output

Description The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when th

Octal Transparent Latch with 3-State Output

Description The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when th

Octal Transparent Latch with 3-State Output

Description The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when th

Octal Transparent Latch with 3-State Output

Description The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when th

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While t