Rad-hard high voltage CMOS logic series

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Rad-hard, high voltage, CMOS logic series

Features • ESCC qualified • 18 V Absolute maximum ratings • 3 V to 15 V operating voltage • Hermetic packages • Rad-hard 100 krad (Si) TID • SEL immune up to 119 MeV.cm²/mg • SEU immune up to 119 MeV.cm²/mg • -55 °C to +125 °C temperature range • ESCC specification available on ESCC websi

Rad-hard, high voltage, CMOS logic series

Features • ESCC qualified • 18 V Absolute maximum ratings • 3 V to 15 V operating voltage • Hermetic packages • Rad-hard 100 krad (Si) TID • SEL immune up to 119 MeV.cm²/mg • SEU immune up to 119 MeV.cm²/mg • -55 °C to +125 °C temperature range • ESCC specification available on ESCC websi

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

CMOS DUAL UP-COUNTERS

CMOS DUAL UP-COUNTERS

CMOS DUAL UP-COUNTERS

Dual BCD Up Counter, Dual Binary Up Counter

Dual binary counter

Dual binary counter

Dual Up Counters

CMOS DUAL UP COUNTERS

Dual Binary Up Counter

DUAL BINARY UP COUNTER