Rad-hard high voltage CMOS logic series

文件：303.47 Kbytes Page：24 Pages

Rad-hard, high voltage, CMOS logic series

Features • ESCC qualified • 18 V Absolute maximum ratings • 3 V to 15 V operating voltage • Hermetic packages • Rad-hard 100 krad (Si) TID • SEL immune up to 119 MeV.cm²/mg • SEU immune up to 119 MeV.cm²/mg • -55 °C to +125 °C temperature range • ESCC specification available on ESCC websi

Rad-hard, high voltage, CMOS logic series

Features • ESCC qualified • 18 V Absolute maximum ratings • 3 V to 15 V operating voltage • Hermetic packages • Rad-hard 100 krad (Si) TID • SEL immune up to 119 MeV.cm²/mg • SEU immune up to 119 MeV.cm²/mg • -55 °C to +125 °C temperature range • ESCC specification available on ESCC websi

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

Dual JK flip-flop

DUAL-J-K MASTER-SLAVE FLIP-FLOP

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CMOS Dual J-K Master-Slave Flip-Flop

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CMOS Dual J-K Master-Slave Flip-Flop

CMOS Dual J-K Master-Slave Flip-Flop

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

DUAL-J-K MASTER-SLAVE FLIP-FLOP

Dual J-K Flip Flop

Dual JK flip-flop

Dual JK flip-flop

Dual JK flip-flop

Dual J-K Flip-Flop

Dual J-K Flip-Flop

Dual J-K Flip-Flop

Dual J−K Flip−Flop

COMPLEMENTARY METAL OXIDE SILICON

DUAL D TYPE FUP FLOP

DUAL J-K MASTER-SLAVE FLIP FLOP

DUAL J-K MASTER-SLAVE FLIP FLOP

Dual J-K Master-Slave Flip Flop