22-bit GTL processor voltage clamp

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

NXP bidirectional low-voltage translators

NXP bidirectional low-voltage translators

NXP bidirectional low-voltage translators

22-bit GTL processor voltage clamp

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

NXP bidirectional low-voltage translators

NXP bidirectional low-voltage translators

2-bit bi-directional low voltage translator

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

2-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

2-bit bi-directional low voltage translator

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

2-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

2-bit bi-directional low voltage translator

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

2-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

2-bit bi-directional low voltage translator

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

2-bit bidirectional low voltage translator

2-bit bidirectional low voltage translator

2-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

NXP bidirectional low-voltage translators

2-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

8-bit bidirectional low voltage translator

General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor

8-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

8-bit bidirectional low voltage translator

General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor

8-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

8-bit bidirectional low voltage translator

General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor

8-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

NXP bidirectional low-voltage translators

Quad GTL/GTL to LVTTL/TTL bidirectional latched translator

DESCRIPTION The GTL2004 is a quad translating transceiver designed for 3.3V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. Separate latch enables allow sampling and holding of data from th

Quad GTL/GTL to LVTTL/TTL bidirectional latched translator

DESCRIPTION The GTL2004 is a quad translating transceiver designed for 3.3V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. Separate latch enables allow sampling and holding of data from th

Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

DESCRIPTION The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. FEATURES • Operates as a quad GTL/GTL+ sampling receiver or as

Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

DESCRIPTION The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. FEATURES • Operates as a quad GTL/GTL+ sampling receiver or as

Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

DESCRIPTION The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. FEATURES • Operates as a quad GTL/GTL+ sampling receiver or as

13-bit GTL-/GTL/GTL to LVTTL translator

DESCRIPTION The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the Xeon processor GTL–/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications. FEATURES • Operates as a GTL–/GTL/GTL+ to LVTTL sampling receiver or

13-bit GTL-/GTL/GTL to LVTTL translator

DESCRIPTION The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the Xeon processor GTL–/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications. FEATURES • Operates as a GTL–/GTL/GTL+ to LVTTL sampling receiver or

13-bit GTL to LVTTL translator with power good control

General description The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. Features ■ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver ■ 3.0 V to 3.6 V operation ■ LVTTL I/O not 5

12-bit GTL to LVTTL translator with power good control

13-bit GTL to LVTTL translator with power good control

General description The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. Features ■ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver ■ 3.0 V to 3.6 V operation ■ LVTTL I/O not 5

12-bit GTL to LVTTL translator with power good control

12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs

General description The GTL2008/GTL2107 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. Features ■ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver ■ EN1 and EN2 disable error output ■

12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs

12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs

General description The GTL2008/GTL2107 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. Features ■ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver ■ EN1 and EN2 disable error output ■

12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs

10-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

10-bit GTL Processor Voltage Clamp

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

10-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

10-bit GTL Processor Voltage Clamp

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with

10-bit bidirectional low voltage translator

NXP bidirectional low-voltage translators

10-bit GTL Processor Voltage Clamp

Description Within the semiconductor world, there are many I/O standards that have different voltage level requirements for the input voltage (VIH or VIL) and output voltage (VOH or VOL) typically based on the device operating voltage. These voltage levels define how the device communicates with